In general, the invention relates to processing of semiconductor wafers and has particular applicability to formation of interconnect elements on semiconductor devices while in wafer form.
As is known, microelectronic or integrated circuits are manufactured by forming identical such circuits on each of a many devices or dice on a semiconductor wafer. Eventually, the wafer is divided or xe2x80x9csingulatedxe2x80x9d into the individual devices or dice. Typically, this involves cutting, e.g., using a very fine saw, laser, kerfing tool, dicing tool, or the like, the wafer along spaces between the dice, which spaces customarily are referred to as xe2x80x9cscribe streetsxe2x80x9d or xe2x80x9ckerf lines.xe2x80x9d
Each of the individual die on a wafer include terminals that function as connection points into and out of the microelectronic circuit on the die. Eventually, interconnect elements are attached to the terminals. In use, these interconnect elements form electrical connections with an external element, allowing the external element and the die to communicate electrically. Examples of such external elements include without limitation printed circuit boards, other die, and other electronic elements.
Commonly used interconnect elements include metal pins, solder balls, metal bumps, and metal pads. Resilient, elongated, spring-type interconnect elements, which have recently been developed, may also be used. Examples of such interconnect elements are described in this application and in applications incorporated herein by reference.
Many, but not all, semiconductor devices (i.e., die) are also packaged. That is, a protective material is formed on or around at least a portion of the die. The protective material may serve a number of functions, including without limitation protecting the die, strengthening the die, and dissipating heat generated by the die. Plastics, metals, ceramics, resins, and organic materials are nonexclusive examples of commonly used packaging materials. Of course, the interconnect elements attached to a die""s terminals must extend through the die""s packaging.
Traditionally, a wafer is singulated into individual die before interconnect elements are attached to the dice""s terminals and before the dice are packaged. It is known, however, to attach interconnect elements to the terminals of a die and/or package the die while the die is still in wafer form (that is, before the wafer has been singulated). This is sometimes referred to as xe2x80x9cwafer level packaging.xe2x80x9d
According to conventional wisdom, the interconnect elements and the packaging materials formed on a die of an unsingulated wafer must be located entirely within the boundary of the die on the wafer. That is, neither the interconnect elements nor the packaging materials may extend beyond the boundary of the die into the scribe streets surrounding the die. This limitation arises primarily because such interconnect elements or packaging materials would interfere with any subsequent attempt to cut the wafer along its scribe streets.
That interconnect elements and packaging materials are confined to the area of the die imposes disadvantages on the use of wafer level packaging. One such disadvantage is a corresponding restriction on the pitch and layout of the interconnect elements. Simply put, the pitch of interconnect elements located entirely within the boundary of a die must be finer or tighter than the pitch of interconnect elements that fan out beyond the boundary of the die (as is the case where the interconnect elements are attached to the die after it has been singulated from the wafer). Of course, the finer the pitch of the interconnect elements on the die, the finer the pitch that is required of the connection receptacles on the external element (e.g., printed circuit board) to which the die will be connected in use. Generally speaking, the finer the pitch of the connection receptacles, the greater the cost of the external element.
Similarly, requiring that the interconnect elements be confined entirely within the boundary of the die also limits the pattern or layout of the interconnect elements. That is, the greater the area in which the interconnect elements can be located, the more freedom there is in locating each interconnect element and therefore the more freedom there is in selecting the pattern or layout of the interconnect elements. Again, the loss of such freedom associated with wafer level packaging increases costs.
As should be apparent, a way of packaging a diexe2x80x94and in particular, of attaching interconnect elements to terminals of the diexe2x80x94while in wafer form that allows the interconnect elements to fan out beyond the boundaries of the die is needed.
The present invention relates to processing of semiconductor devices while in wafer form and more particularly to formation of interconnect elements that fan out beyond the boundary of a die. An unsingulated semiconductor wafer is provided. Electrical interconnect elements are formed on the unsingulated wafer such that the interconnect elements are electrically connected to terminals of the semiconductor dice composing the wafer. At least a portion of the interconnect elements extend beyond the boundaries of the dice into the scribe streets separating the individual dice. Thereafter, the wafer is singulated into individual dice.